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TDA9109/SN
LOW-COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
PRELIMINARY DATA
I2C GEOMETRY CORRECTIONS VERTICAL PARABOLA GENERATOR (Pin Cushion - E/W, Keystone, Corner) HORIZONTAL DYNAMIC PHASE (Side Pin Balance & Parallelogram) VERTICAL DYNAMIC FOCUS (Vertical Focus Amplitude) GENERAL SYNC PROCESSOR 12V SUPPLY VOLTAGE 8V REFERENCE VOLTAGE HOR. & VERT. LOCK/UNLOCK OUTPUTS READ/WRITE I 2C INTERFACE HORIZONTAL AND VERTICAL MOIRE B+ REGULATOR - INTERNAL PWM GENERATOR FOR B+ CURRENT MODE STEP-UP CONVERTER - SOFT START 2 - I C ADJUSTABLEB+ REFERENCE VOLTAGE - OUTPUT PULSES SYNCHRONIZED ON HORIZONTAL FREQUENCY - INTERNALMAXIMUMCURRENT LIMITATION COMPARED WITH THE TDA9109, THE TDA9109/SN HAS : - CORNER CORRECTION, - HORIZONTAL MOIRE,
. . . . . . . . . . . . . . . . . . . . .
HORIZONTAL SELF-ADAPTATIVE DUAL PLL CONCEPT 150kHz MAXIMUM FREQUENCY X-RAY PROTECTION INPUT I2C CONTROLS : H-POSITION, FREQUENCY GENERATOR FOR BURN-IN MODE VERTICAL VERTICAL RAMP GENERATOR 50 TO 185Hz AGC LOOP GEOMETRY TRACKING WITH VPOS & VAMP I2C CONTROLS : VAMP, VPOS, S-CORR, C-CORR DC BREATHING COMPENSATION
SHRINK32 (Plastic Package) ORDER CODE : TDA9109/SN
B+ SOFT START, INCREASED MAX.VERTICAL FREQUENCY, NO HORIZONTAL FOCUS, NO STEP DOWN OPTION FOR DC/DC CONVERTER, - NO I2C FREE RUNNING ADJUSTMENT, - FIXED HORIZONTAL DUTY CYCLE (48%), - INCREASED MAXIMUM STORAGE TIME OF THE HORIZONTAL SCANNING TRANSISTOR. DESCRIPTION The TDA9109/SN is a monolithic integrated circuit assembledin 32-pin shrink dual in line plastic package. This IC controls all the functions related to the horizontal and vertical deflection in multimode or multi-frequency computer display monitors. The internal sync processor, combinedwith the very powerful geometry correction block make the TDA9109/SN suitable for very high performance monitors, using very few external components. The horizontaljitter level is very low. It is particularly well suited for high-end 15" and 17" monitors. Combined with the ST7275 Microcontroller family, TDA9206 (Video preamplifier) and STV942x (On-Screen Display controller) the TDA9109/SN allows fully I2 C bus controlled computer display monitors to be built with a reduced number of external components.
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June 1998
This is advance information on a new product now in development or undergoing evaluatio n. Details are subject to change without notice.
TDA9109/SN
PIN CONNECTIONS
H/HVIN VSYNCIN HLOCKOUT PLL2C C0 R0 PLL1F HPOSITION HMOIRE FOCUS-OUT HGND HFLY HREF COMP REGIN ISENSE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 5V SDA SCL VCC BOUT GND HOUT XRAY EWOUT VOUT VCAP VREF VAGCCAP VGND
9109SN01.EPS
BREATH B+GND
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TDA9109/SN
PIN CONNECTIONS
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 26 25 27 28 29 30 31 32 Name H/HVIN VSYNCIN HLOCKOUT PLL2C C0 R0 PLL1F HPOSITION HMOIRE FOCUSOUT HGND HFLY HREF COMP REGIN ISENSE B+GND BREATH VGND VAGCCAP VREF VCAP VOUT EWOUT HOUT XRAY GND BOUT VCC SCL SDA 5V Function TTL compatible Horizontal sync Input (separate or composite) TTL compatible Vertical sync Input (for separated H&V) First PLL Lock/Unlock Output (0V unlocked - 5V locked) Second PLL Loop Filter Horizontal Oscillator Capacitor Horizontal Oscillator Resistor First PLL Loop Filter Horizontal Position Filter (capacitor to be connected to HGND) Horizontal Moire Output (to be connected to PLL2C through a resistor divider) Vertical Dynamic Focus Output Horizontal Section Ground Horizontal Flyback Input (positive polarity) Horizontal Section Reference Voltage (to be filtered) B+ Error Amplifier Output for frequency compensation and gain setting Regulation Input of B+ control loop Sensing of external B+ switching transistor current Ground (related to B+ reference adjustment) DC Breathing Input Control (compensation of vertical amplitude against EHV variation) Vertical Section Ground Memory Capacitor for Automatic Gain Control Loop in Vertical Ramp Generator Vertical Section Reference Voltage (to be filtered) Vertical Sawtooth Generator Capacitor Vertical Ramp Output (with frequency independant amplitude and S or C Corrections if any). It is mixed with vertical position voltage and vertical moire. Pin Cushion - E/W Correction Parabola Output Horizontal Drive Output (internal transistor, open collector) X-RAY protection input (with internal latch function) General Ground (referenced to VCC) B+ PWM Regulator Output Supply Voltage (12V typ) I2C Data Input Supply Voltage (5V typ.)
9109SN01.TBL
I2C Clock Input
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TDA9109/SN
QUICK REFERENCE DATA
Parameter Horizontal Frequency Autosynch Frequency (for given R0 and C0) Horizontal Sync Polarity Input Polarity Detection (on both Horizontal and Vertical Sections) TTL Composite Sync Lock/Unlock Identification (on both Horizontal 1st PLL and Vertical Section) I2C Control for H-Position XRAY Protection I2C Horizontal Duty Fixed I2C Free Running Frequency Adjustment Stand-by Function Dual Polarity H-Drive Outputs Supply Voltage Monitoring PLL1 Inhibition Possibility Blanking Outputs Vertical Frequency Vertical Autosync (for 150nF on Pin 22 and 470nF on Pin 20) Vertical S-Correction Vertical C-Correction Vertical Amplitude Adjustment DC Breathing Control on Vertical Amplitude Vertical Position Adjustment East/West (E/W) Parabola Output (also known as Pin Cushion Output) E/W Correction Amplitude Adjustment Keystone Adjustment Corner Correction Internal Dynamic Horizontal Phase Control Side Pin Balance Amplitude Adjustment Parallelogram Adjustment Tracking of Geometric Corrections with Vertical Amplitude and Position Reference Voltage (both on Horizontal and Vertical) Vertical Dynamic Focus I C Horizontal Dynamic Focus Amplitude Adjustment I2C Horizontal Dynamic Focus Symmetry Adjustment I2C Vertical Dynamic Focus Amplitude Adjustment Detection of Input Sync Type Vertical Moire Output Horizontal Moire Output I C Controlled Moire Amplitude Frequency Generator for Burn-in Fast I C Read/Write B+ Regulation adjustable by I2C B+ Soft Start
2 2 2
Value 15 to 150 1 to 4.5 f0 YES YES YES YES 10 YES 48 NO YES NO YES NO NO 35 to 200 50 to 185 YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES NO NO YES YES YES YES YES YES YES YES 400
Unit kHz
% %
Hz Hz
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9109SN02.TBL
kHz
HOUT
HLOCKOUT
HPOSITION HFLY PLL2C R0 C0 8 3 6 5 12 4 26 VCO
BLOCK DIAGRAM
PLL1F 7
HREF 13
VREF
HGND 11 Forced Frequency 2 bits SAFETY PROCESSOR LOCK/UNLOCK IDENTIFICATION B+ Adjust 7 bits X2 VSYNC HSYNC Spin Bal 6 bits X Corner 7 bits X
4
PHASE/FREQUENCY COMPARATOR H-PHASE (7 bits) PHASE COMPARATOR PHASE SHIFTER H-DUTY (48%) HOUT BUFFER
5V VCC XRAY B+ CONTROLLER
14 COMP 28 B+OUT 15 REGIN 16 ISENSE 17 BGND
H/HVIN
1
VSYNCIN
2
SYNC INPUT SELECT (1 bit)
SYNC PROCESSOR
VCC 29
XRAY 25
VERTICAL Parallelogram MOIRE 6 bits CANCEL 5 BITS+ON/OFF GEOMETRY TRACKING 6 bits 6 bits VAMP 7 bits
HORIZONTAL MOIRE CANCEL 5 BITS+ON/OFF
9
HMOIRE
VREF 21
VREF
VGND 19
E/W 7 bits X2 AMPVDF 6 bits Keyst. 6 bits X
10 FOCUS
5V 32 S AND C CORRECTION
RESET GENERATOR VERTICAL OSCILLATOR RAMP GENERATOR
SDA 31
SCL 30
I2C INTERFACE
GND 27 22 20
VPOS 7 bits 18 23 24
TDA9109/SN
VOUT VAGCCAP
EWOUT BREATH
VCAP
TDA9109/SN
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9109SN02.EPS
TDA9109/SN
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VDD VIN Parameter Supply Voltage (Pin 29) Supply Voltage (Pin 32) Max Voltage on Pin 4 Pin 5 Pins 6, 7, 8, 14, 15, 16, 20, 22 Pins 9, 10, 18, 23, 24, 25, 26, 28 Pins 1, 2, 3, 30, 31 ESD susceptibility Human Body Model,100pF Discharge through 1.5k EIAJ Norm, 200pF Discharge through 0 Storage Temperature Junction Temperature Operating Temperature Value 13.5 5.7 4.0 6.4 8.0 VCC VDD 2 300 -40, +150 +150 0, +70 Unit V V V V V V V kV V o C o C o C
VESD Tstg Tj Toper
Symbol Rth (j-a)
Parameter Junction-Ambient Thermal Resistance Max.
Value 65
Unit
o
C/W
SYNC PROCESSOR Operating Conditions (VDD = 5V, T amb = 25oC)
Symbol HsVR MinD Mduty VsVR VSW VSmD VextM IHLOCKOUT Parameter Voltage on H/HVIN Input Minimum Horizontal Input Pulses Duration Maximum Horizontal Input Signal Duty Cycle Voltage on VSYNCIN Minimum Vertical Sync Pulse Width Maximum Vertical Sync Input Duty Cycle Maximum Vertical Sync Width on TTL H/Vcomposite Sink and Source Current Test Conditions Pin 1 Pin 1 Pin 1 Pin 2 Pin 2 Pin 2 Pin 1 Pin3 Min. 0 0.7 0 5 Typ. Max. 5 25 5 15 750 250 Unit V s % V s % s A
Electrical Characteristics (VDD = 5V, Tamb = 25oC)
Symbol VINTH RIN TfrOut VHlock VoutT Parameter Horizontal and Vertical Input Logic Level (Pins 1, 2) Horizontal and Vertical Pull-Up Resistor Fall and Rise Time, Output CMOS Buffer Horizontal 1st PLL Lock Output Status (Pin 3) Extracted Vsync Integration Time (% of TH) on H/V Composite (see Note 1) Test Conditions Low Level High Level Pins 1, 2 Pin 3, COUT = 20pF Locked, ILOCKOUT = -250A Unlocked, I LOCKOUT = +250A C0 = 820pF Min. 2.2 200 0 5 35 200 0.5 Typ. Max. 0.8 Unit V V k ns V V %
4.4 26
Note 1 : TH is the horizontal period.
I2C READ/WRITE (see Note 2) Electrical Characteristics (VDD = 5V,Tamb = 25oC)
Symbol I C PROCESSOR Fscl Tlow Thigh Vinth VACK Maximum Clock Frequency Low period of the SCL Clock High period of the SCL Clock SDA and SCL Input Threshold Acknowledge Output Voltage on SDA input with 3mA Pin 30 Pin 30 Pin 30 Pins 30,31 Pin 31 400 1.3 0.6 2.2 0.4 kHz s s V V
2
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Note 2 : See also I2C Table Control and I2C Sub Address Control.
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9109SN05.TBL
9109SN04.TBL
THERMAL DATA
9109SN03.TBL
TDA9109/SN
HORIZONTAL SECTION Operating Conditions
Symbol VCO R0(Min.) C0(Min.) F(Max.) Minimum Oscillator Resistor Minimum Oscillator Capacitor Maximum Oscillator Frequency Pin 6 Pin 5 6 390 150 k pF kHz Parameter Test Conditions Min. Typ. Max. Unit
OUTPUT SECTION I12m HOI Maximum Input Peak Current Horizontal Drive Output Maximum Current Pin 12 Pin 26, Sunk current 5 30 mA mA
Electrical Characteristics (VCC = 12V, Tamb = 25oC)
Symbol Parameter Test Conditions Min. Typ. Max. Unit SUPPLY AND REFERENCE VOLTAGES VCC VDD ICC IDD VREF-H VREF-V IREF-H IREF-V Supply Voltage Supply Voltage Supply Current Supply Current Horizontal Reference Voltage Vertical Reference Voltage Max. Sourced Current on VREF-H Max. Sourced Current on VREF-V Pin 29 Pin 32 Pin 29 Pin 32 Pin 13, I = -2mA Pin 21, I = -2mA Pin 13 Pin 21 7.4 7.4 10.8 4.5 12 5 50 5 8 8 8.6 8.6 5 5 13.2 5.5 V V mA mA V V mA mA
1st PLL SECTION HpolT VVCO Vcog Hph Vbmin Vbtyp Vbmax IPll1U IPll1L f0 df0/dT CR Delay Time for detecting polarity change (see Note 3) VCO Control Voltage (Pin 7) VCO Gain (Pin 7) Horizontal Phase Adjustment (see Note 4) Horizontal Phase Setting Value (Pin 8) (see Note 4) Minimum Value Typical Value Maximum Value PLL1 Filter Current Charge Free Running Frequency Free Running Frequency Thermal Drift (No drift on external components) (see Note 5) PLL1 Capture Range R0 = 6.49k, C 0 = 820pF, from f0+0.5kHz to 4.5f0 fH(Min.) fH(Max.) FF1 Byte 11xxxxxx FF2 Byte 10xxxxxx Sub-Address 02 Pin 1 VREF-H = 8V f0 fH(Max.) 0.75 1.3 6.2 17.1 10 2.8 3.4 4.0 140 1 22.8 -150 ms V V kHz/V % V V V A mA kHz ppm/C
R0 = 6.49k, C 0 = 820pF, dF/dV = 1/11R0C 0 % of Horizontal Period Sub-Address 01 Byte x1111111 Byte x1000000 Byte x0000000 PLL1 is Unlocked PLL1 is Locked R0 = 6.49k, C 0 = 820pF, f0 = 0.97/8R0C 0
90 2f0 3f0
FF
Notes : 3. 4. 5. 6.
Forced Frequency
This delay is mandatory to avoid a wrong detection of polarity change in the case of a composite sync. See Figure 10 for explanation of reference phase. These parameters are not tested on each unit. They are measured during our internal qualification. This PLL capture range may be obtained only if f0 is captured (for instance bu adjusting R0). If not, more margin must be provided between fH (Min.) and f0, to cope with the components spread.
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9109SN05.TBL
25
kHz kHz
TDA9109/SN
HORIZONTAL SECTION (continued) Electrical Characteristics (VCC = 12V, Tamb = 25oC) (continued)
Symbol Parameter Test Conditions Min. Typ. Max. Unit 2nd PLL SECTION AND HORIZONTAL OUTPUT SECTION FBth Hjit HD XRAYth Vphi2 VSCinh Flyback Input Threshold Voltage (Pin 12) Horizontal Jitter Horizontal Drive Output Duty-Cycle (Pin 26) (see Note 7) X-RAY Protection Input Threshold Voltage Internal Clamping Levels on 2nd PLL Loop Filter (Pin 4) Threshold Voltage to Stop H-Out,V-Out, B-Out and Reset XRAY when VCC < VSCinh (see Note 8) Threshold Voltage to Stop H-Out,V-Out, B-Out and Reset XRAY when VDD < VSDinh Horizontal Drive Output (low level) Pin 25, see Note 8 Low Level High Level Pin 29 At 31.4kHz 0.65 0.75 70 48 8 1.6 4.0 7.5 V ppm % V V V V
VSDinh
Pin 32
4.0
V
HDvd
Pin 26, IOUT = 30mA
0.4
V
VERTICAL DYNAMIC FOCUS FUNCTION (positive parabola) HDFDC TDHDF AMPVDF Bottom DC Output Level DC Output Voltage Thermal Drift (see Note 5) Vertical Dynamic Focus Parabola Amplitude with VAMP and VPOS Typical Min. Byte 000000 Typ. Byte 100000 Max. Byte 111111 Sub-Address 0F 0 0.5 1 0.6 1 1.5 0.52 0.52 VPP VPP VPP VPP VPP VPP VPP VPP
9109SN05.TBL
RLOAD = 10k, Pin 10
2 200
V ppm/C
VDFAMP
Parabola Amplitude Function of VAMP Sub-Address 05 (tracking between VAMP and VDF) with Byte 10000000 VPOS Typ. (see Figure 1 and Note 9) Byte 11000000 Byte 11111111
VHDFKeyt Parabola Asymetry Function of VPOS Sub-Address 06 Control (tracking between VPOS and VDF) Byte x0000000 with VAMP Max. Byte x1111111
Notes : 5. These parameters are not tested on each unit. They are measured during our internal qualification. 7. Duty Cycle is the ratio between the output transistor OFF time and the period. The power transistor is controlled OFF when the output transistor is OFF. 7. Initial Condition for Safe Operation Start Up 8. See Figure 14. 9. S and C correction are inhibited so the output sawtooth has a linear shape.
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TDA9109/SN
VERTICAL SECTION Operating Conditions
Symbol OUTPUTS SECTION VEWM VEWm R LOAD Maximum E/W Output Voltage Minimum E/W Output Voltage Minimum Load for less than 1% Vertical Amplitude Drift Pin 24 Pin 24 Pin 20 1.8 65 6.5 V V M Parameter Test Conditions Min. Typ. Max. Unit
Electrical Characteristics (VCC = 12V, Tamb = 25oC)
Symbol VERTICAL RAMP SECTION VRB VRT VRTF VSTD VFRF ASFR RAFD Rlin VPOS Voltage at Ramp Bottom Point Voltage at Ramp Top Point (with Sync) Voltage at Ramp Top Point (without Sync) Vertical Sawtooth Discharge Time Vertical Free Running Frequency (see Note 10) AUTO-SYNC Frequency (see Note 11) VREF-V = 8V, Pin 22 VREF-V = 8V, Pin 22 Pin 22 Pin 22, C22 = 150nF C OSC (Pin 22) = 150nF Measured on Pin22 C22 = 150nF 5% 50 200 0.5 3.2 3.5 3.8 2.25 3 3.75 5 Sub Address 07 V/VPP at TV/4 V/VPP at 3TV/4 Sub Address 08 V/VPP @ TV/2 Byte x1000000 Byte x1100000 Byte x1111111 -4 +4 % %
9109SN05.TBL
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
2 5 VRT-0.1 70 100 185
V V V s Hz Hz ppm/Hz % 3.3 V V V V V V mA
Ramp Amplitude Drift Versus Frequency at C 22 = 150nF 50Hz < f and f < 185Hz Maximum Vertical Amplitude (see Note 5) Ramp Linearity on Pin 22 (see Note 10) Vertical Position Adjustment Voltage (Pin 23 - VOUT mean value) 2.5V < V27 and V27 < 4.5V Sub Address 06 Byte x0000000 Byte x1000000 Byte x1111111 Sub Address 05 Byte x0000000 Byte x1000000 Byte x1111111
3.65
VOR
Vertical Output Voltage (peak-to-peak on Pin 23)
2.5
3.5
VOI dVS
Vertical Output Maximum Current (Pin 23) Max Vertical S-Correction Amplitude (see Note 12) x0xxxxxx inhibits S-CORR x1111111 gives max S-CORR Vertical C-Corr Amplitude x0xxxxxx inhibits C-CORR
Ccorr
-3 0 3
% % %
Notes : 5. These parameters are not tested on each unit. They are measured during our internal qualification. 10. With Register 07 at Byte x0xxxxxx (S correction is inhibited) and with Register 08 at Byte x0xxxxxx (C correction is inhibited), the sawtooth has a linear shape. 11. This is the frequency range for which the vertical oscillator will automatically synchronize, using a single capacitor value on Pin 22 and with a constant ramp amplitude. 12. TV is the vertical period.
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TDA9109/SN
VERTICAL SECTION (continued) Electrical Characteristics (VCC = 12V, Tamb = 25oC) (continued)
Symbol East/West (E/W) FUNCTION EWDC TDEW DC EWpara DC Output Voltage with Typ. VPOS, Keystone and Corner inhibited DC Output Voltage Thermal Drift Parabola Amplitude with Max. VAMP, Typ. VPOS, Keystone and Corner inhibited Pin 24, see Figure 2 See Note 13 Subaddress 0A Byte 11111111 Byte 11000000 Byte 10000000 Subaddress 05 Byte 10000000 Byte 11000000 Byte 11111111 Subaddress 09 Byte 1x000000 Byte 1x111111 Subaddress 06 2.5 100 1.7 0.85 0 0.30 0.55 0.85 0.65 0.65 V ppm/C VPP VPP VPP VPP VPP VPP VPP VPP Parameter Test Conditions Min. Typ. Max. Unit
EWtrack
Parabola Amplitude Function of VAMP Control (tracking between VAMP and E/W) with Typ. VPOS, Typ. E/W Amplitude, Keystone and Corner inhibited (see Note 10) Keystone Adjustment Capability with Typ. VPOS, Corner and E/W inhibited and Max. Vertical Amplitude (see Note 10 and Figure 4) Intrinsic Keystone Function of VPO S Control (tracking between VPOS and E/W) with Max. E/W Amplitude,Max. Vertical Amplitude and Corner inhibited (see Note 13 and Figure 2) A/B Ratio B/A Ratio Corner Amplitude with Max. VAMP, Typ. VPOS, Keystone and E/W inhibited
KeyAdj
KeyTrack
Byte x0000000 Byte x1111111 Subaddress 0B Byte 11111111 Byte 11000000 Byte 10000000
0.52 0.52 1.7 0 -1.7 VPP VPP VPP
Corner
INTERNAL DYNAMIC HORIZONTAL PHASE CONTROL SPBpara Side Pin Balance Parabola Amplitude (Figure 3) with Max. VAMP, Typ. VPOS and Parallelogram inhibited (see Notes 10 & 14) Side Pin Balance Parabola Amplitude function of VAMP Control (tracking between VAMP and SPB) with Max. SPB, Typ. VPOS and Parallelogram inhibited (see Notes 10 & 14) P ara ll elo gr am A dju st men t Capa bilit y w ith M ax . V AM P , T yp . VP O S a n d M a x. S PB (see Notes 10 & 14) Intrinsic Parallelogram Function of VPOS Control ( tracki ng be tween VPO S and DHPC) with Max. VAMP, Max. SPB and Parallelogram inhibited (see Notes 10 & 14) A/B Ratio B/A Ratio Subaddress 0D Byte x1111111 Byte x1000000 Subaddress 05 Byte 10000000 Byte 11000000 Byte 11111111 Subaddress 0E Byte x1111111 Byte x1000000 Subaddress 06 +1.4 -1.4 0.5 0.9 1.4 +1.4 -1.4 %TH %TH %TH %TH %TH %TH %TH
SPBtrack
ParAdj
Partrack
Byte x0000000 Byte x1111111
0.52 0.52
VERTICAL MOIRE VMOIRE Vertical Moire (measured on VOUT : Pin 23) Subaddress 0C Byte 01x11111 6 mV
9109SN05.TBL
BREATHING COMPENSATION BRRANG BRADj DC Breathing Control Range (see Note 15) Vertical Output Variation versus DC Breathing Control (Pin 23) V18 V18 VREF-V V18 = 4V 1 0 -10 12 V % %
Notes : 10. With Register 07 at Byte x0xxxxxx (S correction is inhibited) and with Register 08 at Byte x0xxxxxx (C correction is inhibited), the sawtooth has a linear shape. 13. These parameters are not tested on each unit. They are measured during our internal qualification. 14. TH is the horizontal period. 15. When not used the DC breathing control pin must be connected to 12V.
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TDA9109/SN
B+ SECTION Operating Conditions
Symbol Parameter Test conditions Resistor between Pins 15 and 14 Min. 5 Typ. Max. Unit k FeedRes Minimum Feedback Resistor
Electrical Characteristics (VCC = 12V, Tamb = 25oC)
Symbol OLG ICOMP Parameter Error Amplifier Open Loop Gain Test conditions At low frequency (see Note 16) Min. Typ. 85 0.5 Max. Unit dB mA
Sunk Current on Error Amplifier Pin 14 (see Figure 14) Output when BO UT is in safety condition Unity Gain Bandwidth Regulation Input Bias Current Error Amplifier Output Current Current Sense Input Voltage Gain (see Note 13) Current sourced by Pin 15 (PNP base) Current sourced by Pin 14 Current sunk by Pin 14 Pin 16
UGBW IRI EAOI CSG MCEth ISI Tonmax B+OSV IVREF VREFADJ tFB+
6 0.2 0.5 2 3 1.2 1 100 0.25 4.8 +20 -20 100
MHz A mA mA V A % V V % % ns
9109SN05.TBL 9109SN06.EPS 9109SN04.EPS
Max Current Sense Input Threshold Pin 16 Voltage Current Sense Input Bias Current Current sourced by Pin 16 (PNP base) Maximum ON Time of the external % of Horizontal period, power transistor f0 = 27kHz (see Note 17) B+ Output Saturation Voltage Internal Reference Voltage I nt e rna l R e fe r en ce Adjustment Range Fall Time V28 with I28 = 10mA On erroramp (+) inputfor Subaddress 0B Byte 1000000 V ol tag e Byte 1111111 Byte 0000000 Pin 28
Notes : 13. These parameters are not tested on each unit. They are measured during our internal qualification. 16. These parameters are not tested on each unit. They are measured during our internal qualification procedure which includes characterization on batches coming from corners of our processes and also temperature characterization. 17. The external power transistor is OFF during about 400ns.
Figure 1 : Vertical Dynamic Focus Function
Figure 2 : E/W Output
VDFAMP A
B
A
9109SN03.EPS
B EWPARA
HDFDC
EWDC
Figure 3 :
Dynamic Horizontal Phase Control Output
Figure 4 :
Keystone Effect on E/W Output (PCC and Corner Inhibited)
B A
Keyadj
9109SN05.EPS
SPBPARA
DHPCDC
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TDA9109/SN
TYPICAL VERTICAL OUTPUT WAVEFORMS
Function Sub Address Pin Byte
VOUTDC
Specification
Effect on Screen
2.25V
10000000 Vertical Size 05 23
VOUTDC
11111111
3.75V
Vertical Position DC Control
06
23
x0000000 x1000000 x1111111
VOUTDC = 3.2V VOUTDC = 3.5V VOUTDC = 3.8V
0xxxxxxx Inhibited Vertical S Linearity 07 23 1x111111
VPP V = 4% V PP
9109SN06.TBL / 9109SN07.EPS TO 9109SN13.EPS
V
1x000000 Vertical C Linearity 08 23
VPP
V V = 3% V PP V
1x111111
VPP V = 3% V PP
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TDA9109/SN
GEOMETRY OUTPUT WAVEFORMS
Function Sub Address Pin Byte E/W+ Corner inhibited 1x000000 Keystone (Trapezoid) Control 09 24 1x111111
0.65V 2.5V
Specification
Effect on Screen
0.65V
2.5V
E/W (Pin Cushion) Control
Keystone + Corner inhibited 10000000 0A 24 11111111
2.5V
0V
1.7V
Keystone+ E/W inhibited
1.7V
11111111 Corner Control 0B 24 10000000
2.5V
1.7V
SPB inhibited Parrallelogram Control 1x000000 0E Internal 1x111111
3.7V 1.4% TH 3.7V 1.4% TH
Parallelogram inhibited Side Pin Balance Control 1x000000 0D Internal 1x111111
3.7V 1.4% TH
9109SN07.TBL / 9109SN14.EPS TO 9109SN24.EPS
1.4% TH 3.7V
Vertical Dynamic Focus
0F
10
2V TV
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TDA9109/SN
I2C BUS ADDRESS TABLE Slave Address (8C) : Write Mode Sub Address Definition
D8 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Horizontal Drive Selection Horizontal Position Forced Frequency Sync Priority / Horizontal Moire Amplitude Refresh / B+ Reference Adjustment Vertical Ramp Amplitude Vertical Position Adjustment S Correction C Correction E/W Keystone E/W Amplitude E/W Corner Adjustment Vertical Moire Amplitude Side Pin Balance Parallelogram Vertical Dynamic Focus Amplitude
Slave Address (8D) : Read Mode No sub address needed.
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TDA9109/SN
I2C BUS ADDRESS TABLE (continued)
D8 WRITE MODE 00 Xray 1, reset [0] HDrive 0, off [1], on Horizontal Phase Adjustment [1] [0] [0] [0] [0] [0] [0] D7 D6 D5 D4 D3 D2 D1
01
02
03
Forced Frequency 1, on 1, f0 x 2 [0], off [0], f0 x 3 Sync HMoire 0, Comp 1, on [1], Sep [0] Detect Refresh [0], off Vramp 0, off [1], on [1] [0]
Horizontal Moire Amplitude [0] [0] B+ Reference Adjustment [0] [0] [0] [0] [0] [0] [0] [0]
04
Vertical Ramp Amplitude Adjustment [1] [1] [0] [0] [1] [0] [0] [0] [0] [0] [0] [0] [0] [0]
05 06 07
S Select 1, on [0] C Select 1, on [0] E/W Key 0, off [1] [1] E/W Cor 0, off [1] Test V 1, on [0], off SPB Sel 0, off [1] Parallelo 0, off [1] Test H 1, on [0], off [1] VMoire 1, on [0]
Vertical Position Adjustment [0] [0] [0] S Correction [0] [0] [0]
C Correction [1] [0] [0] [0] [0] [0]
08
E/W Keystone [1] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0]
09 0A 0B
E/W Amplitude [0] [0] [0] E/W Corner Adjustment [0] [0] [0] Vertical Moire Amplitude [0] [0] [0]
0C
[0]
[0]
Side Pin Balance [1] [0] [0] [0] [0] [0]
0D
Parallelogram [1] [1] [0] [0] [0] [0] [0]
0E
Vertical Dynamic Focus Amplitude [0] [0] [0] [0] [0]
0F
READ MODE Hlock 0, on [1], no
[ ] initial value
Vlock 0, on [1], no
Xray 1, on [0], off
Polarity Detection V pol H/V pol [1], negative [1], negative
Vext det [0], no det
Sync Detection H/V det V det [0], no det [0], no det
Data is transferred with vertical sawtooth retrace. We recommend to set the unspecified bit to [0] in order to assure the compatibility with future devices.
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TDA9109/SN
OPERATING DESCRIPTION I - GENERAL CONSIDERATIONS I.1 - Power Supply The typical values of the power supply voltages VCC and VDD are 12V and 5V respectively. Optimum operation is obtained for VCC between 10.8 and 13.2V and VDD between 4.5 and 5.5V. Inorderto avoiderraticoperationof thecircuit during the transient phase of VCC and VDD switching on, or off, the value of VCC and VDD are monitored : if VCC is less than 7.5V typ. or if VDD is less than 4.0V typ., the outputs of the circuit are inhibited. Similarly, beforeVDD reaches4V, all the I2C register are reset to their default value. In order to have very good power supply rejection, the circuit is internally supplied by several voltage references (typ. value : 8V). Two of these voltage references are externally accessible, one for the vertical and one for the horizontal part. They can be used to bias external circuitry (if ILOAD is less than 5mA). It is necessary to filter the voltagereferences by externalcapacitorsconnectedto ground,in order to minimize the noise and consequently the "jitter" on vertical and horizontal output signals. I.2 - I2C Control TDA9109/SN belongs to the I 2C controlled device family. Instead of being controlled by DC voltages on dedicated control pins, each adjustment can be done via the I2C Interface. The I2C bus is a serial bus with a clock and a data input. Thegeneral functionand thebus protocolare specified in the Philips-bus data sheets. Theinterface (Data and Clock)is a comparatorwith hysteresis ; the thresholds(less then 2.2V on rising edge, more than 0.8V on falling edge with 5V supply) are TTL-compatible. Spikes of up to 50ns are filtered by an integrator and the maximum clock speed is limited to 400kHz. The data line (SDA) can be used bidirectionally. In read-mode the IC sends reply information (1 byte) to the micro-processor. The bus protocol prescribes a full-byte transmission in all cases. The first byte after the start condition is used to transmit the IC-address (hexa 8C for write, 8D for read). I.3 - Write Mode In write mode the second byte sent contains the subaddress of the selected function to adjust (or controlsto affect)and the thirdbyte the corresponding data byte. It is possible to send more than one data byte to the IC. If after the third byte no stop or start condition is detected, the circuit increments automatically by one the momentary subaddressin the subaddress counter (auto-increment mode). So it is possible to transmit immediately the following data bytes without sending the IC address or subaddress.This can be useful to reinitialize all the controls very quickly (flash manner). This procedure can be finished by a stop condition. The circuit has 14 adjustment capabilities : 1 for the horizontal part, 4 for the vertical, 2 for the E/W correction, 2 for the dynamic horizontal phase control,1 for the Moire option, 3 for the horizontal and the vertical dynamic focus and 1 for the B+ reference adjustment. 17 bits are also dedicated to several controls (ON/OFF, Horizontal Forced Frequency, Sync Priority, Detection Refresh and XRAY reset). I.4 - Read Mode During the read mode the second byte transmits the reply information. The reply byte contains the horizontal and vertical lock/unlock status, the XRAY activation status and, the horizontal and vertical polarity detection.It also contains the sync detection status which is used by the MCU to assign the sync priority. A stop conditionalways stops all the activities of the bus decoder and switches to high impedance both the data and clock line (SDA and SCL). See I2C subaddress and control tables. I.5 - Sync Processor T h e in t e rn a l s yn c p ro ce ss o r a llo ws t h e TDA9109/SN to accept : - separated horizontal & vertical TTL-compatible sync signal, - composite horizontal & vertical TTL-compatible sync signal.
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OPERATING DESCRIPTION (continued) I.6 - Sync Identification Status The MCU can read (address read mode : 8D) the status register via the I 2C bus, and then select the sync priority depending on this status. Among other data this register indicates the presence of sync pulses on H/HVIN, VSYNCIN and (when 12V is supplied) whether a Vext has been extracted from H/HVIN. Both horizontaland vertical sync are detected even if only 5V is supplied. In order to choose the right sync priority the MCU may proceed as follows (see I2C Address Table) : - refresh the status register, - wait at least for 20ms (Max. vertical period), - read this status register. Sync priority choice should be :
Vext H/V det det No Yes Sync priority Subaddress 03 (D8) Yes Yes 1 Yes No 0 V det Comment Sync type Separated H & V Composite TTL H&V
horizontal input. It may be positiveornegative (see Figure 5). Figure 5
Using internal integration, both signals are recognized if Z/T < 25%. Synchronization occurs on the leading edge of the internal sync signal. The minimum value of Z is 0.7s. Another integration is able to extract the vertical pulse from compositesync if the duty cycle is higher than 25% (typically d = 35%) (see Figure 6). Figure 6
Ofcourse, when the choice is made, we can refresh the sync detections and verify that the extracted Vsync is present and that no sync type change has occured. The sync processor also gives sync polarity information. I.7 - IC status The IC can inform the MCU about the 1st horizontal PLL and vertical section status (locked or not) and about the XRAY protection (activated or not). Resetting the XRAY internal latch can be done either by decreasing the VCC or VDD supply or directly resetting it via the I2C interface. I.8 - Sync Inputs Both H/HVIN and VSYNCIN inputs are TTL compatible triggers with hysterisis to avoid erratic detection. Both inputs include a pull up resistor connected to VDD. I.9 - Sync Processor Output The sync processor indicates on the HLOCKOUT Pin whether 1st PLL is locked to an incoming horizontal sync. HLOCKOUT is a TTL compatible CMOS output. Its level goes to high when locked. In the same time the D8 bit of the status register is set to 0. This information is mainly used to trigger safety procedures (like reducing B+ value) as soon as a change is detected on the incoming sync. II - HORIZONTAL PART II.1 - Internal Input Conditions A digital signal (horizontal sync pulse or TTL composite) is sent by the sync processor to the
C d d
9109SN26.EPS
TRAMEXT
The last feature performed is the removal of equalization pulses to avoid parasitic pulses on the phase comparator (which would be disturbed by missing or extraneous pulses). II.2 - PLL1 The PLL1 consists of a phase comparator, an external filter and a voltage-controlled oscillator (VCO). The phase comparator is a "phase frequency"type designed in CMOS technology. This kind of phase detector avoids locking on wrong frequencies. It is followed by a "charge pump", composed of two current sources : sunk and sourced (typically I = 1mA when locked and I = 140A when unlocked). This difference between lock/unlock allows smooth catching of the horizontal frequency by PLL1. This effect is reinforced by an internal original slow down system when PLL1 is locked, avoiding the horizontal frequency changing too quickly. The dynamic behaviour of PLL1 is fixed by an external filter which integrates the current of the charge pump. A "CRC" filter is generally used (see Figure 7).
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TDA9109/SN
OPERATING DESCRIPTION (continued) Figure 7
PLL1F
7
1.8k 4.7F
1F
9109SN27.EPS
The PLL1 is internally inhibited during extracted vertical sync (if any) to avoid taking in account missing Figure 8 : Block Diagram
pulses or wrong pulses on phase comparator. The inhibition is done by a switch located between the charge pump and the filter (see Figure 8). The VCO uses an external RC network. It delivers a linear sawtooth obtained by the charge and the discharge of the capacitor, with a current proportional to the current in the resistor. The typical thresholds of the sawtooth are 1.6V and 6.4V. The control voltage of the VCO is between 1.33V and 6V (see Figure 9). The theorical frequency range of this VCO is in the ratio of 1 to 4.5. The effective frequency range ha s to be smaller (1 to 4.2) due to clamp intervention on the filter lowest value.
Lock/Unlock Status LOCKDET High H/HVIN
1
Tramext
PLL1F 7 I2C Forced Frequency
R0 6
C0 5
INPUT INTERFACE
COMP1 E2 Low
CHARGE PUMP
PLL INHIBITION HPOSITION 8 I2C HPOS Adj.
VCO OSC
9109SN28.EPS 9109SN29.EPS
Tramext
PHASE ADJUST
Figure 9 : Details of VCO
I0
I0
2
PLL1F (Loop Filter) 7
6.4V
RS FLIP FLOP
1.6V
6
(1.3V < V7 < 6V) R0
4 I0
5
6.4V C0 1.6V 0 0.875TH TH
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OPERATING DESCRIPTION (continued) Thesync frequencymust always be higherthan the free running frequency. For example, when using a sync range between 24kHz and 100kHz, the suggested free running frequency is 23kHz. This can beobtainedonly byadjustingf0 (forinstance, making R0 adjustable). If no adjustment is possible, more margin must be provided to cope with the components spread : 8% for the IC, 1% for R0, 2 or 5% for C0, leading to 11% or 14% on f0. The same percentage of frequency range will lost at upper end of the range. Another feature is the capability for the MCU to force the horizontal frequency through I2C to 2xf0 or 3xf0 (for burn-in mode or safety requirements). In this case, the inhibition switch is opened, leaving PLL1 free, but the voltage on PLL1 filter is forced to 2.66V (for 2xf0) or 4.0V (for 3xf0). PLL1 ensuresthe coincidencebetween the leading edge of the sync signal and a phase reference obtained by comparison between the sawtooth of the VCO and an internal DC voltage which is I2C adjustable between 2.8V and 4.0V (corresponding to 10%) (see Figure 10). Figure 10 : PLL1 Timing Diagram
H Osc Sawtooth 7/8TH 1/8TH 6.4V 2.8V < Vb < 4.0V Vb 1.6V Phase REF1 H Synchro
Phase REF1 is obtained by comparison between the sawtooth and a DC voltage adjustable between 2.8V and 4.0V. The PLL1 ensures the exact coincidence between the signal phase REF and HSYNC. A TH/10 phase adjustment is possible.
9109SN30.EPS
available on HLOCKOUT (see Sync Processor). When PLL1 is unlocked, it forces HLOCKOUT to high level. The lock/unlock information is also available through the I2C read. II.3 - PLL2 PLL2 ensures a constant position of the shaped flyback signal in comparison with the sawtooth of the VCO, taking into accountthe saturationtime Ts (see Figure 11). Figure 11 : PLL2 Timing Diagram
H Osc Sawtooth 7/8TH 1/8TH 6.4V 4.0V 1.6V
Flyback Internally Shaped Flyback H Drive Ts Duty Cycle
The duty cycle of H-drive is fixed (48%).
9109SN31.EPS
The TDA9109/SN also includes a Lock/Unlock identification block which senses in real time whether PLL1 is locked or not on the incoming horizontal sync signal. The resulting information is
The phase comparator of PLL2 (phase type comparator) is followed by a charge pump (typical output current : 0.5mA). The flyback input consists of an NPN transistor. This input must be current driven. The maximum recommended input current is 5mA (see Figure 12). The duty cycle is fixed (48%). The maximum storage time (Ts Max.) is (0.44TH TFLY/2). Typically, TFLY/TH is around 20% which means that Ts max is around 34% of TH.
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OPERATING DESCRIPTION (continued) II.4 - Output Section The H-drive signal is sent to the output through a shaping stage which also controls the H-drive duty cycle (I 2C adjustable) (see Figure 11). In order to secure the scanning power part operation, the output is inhibited in the following cases : - when VCC or VDD are too low, - when the XRAY protection is activated, - during the Horizontal flyback, - when the HDrive I2C bit control is off. The output stage consists of a NPN bipolar transistor. Only the collector is accessible(see Figure 13). This output stage is intended for "reverse" base control, where setting the output NPN in off-state will control the power scanning transistor in offstate (see Application Diagram). The maximum output current is 30mA, and the corresponding voltage drop of the output VCEsat is 0.4V Max. Obviously the power scanning transistor cannot be directly driven by the integratedcircuit. An interface has to be added between the circuit and the power transistor either of bipolar or MOS type. II.5 - X-RAY Protection The X-Ray protection is activated by application of a high level on the X-Ray input (8V on Pin 25). It inhibits the H-Drive and B+ outputs. This protection is latched ; it may be reset either by VCC or VDD switch off or by I2C (see Figure 14). Figure 14 : Safety Functions Block Diagram
VCC Checking VCC VSCinh VDD Checking VDD VSDinh XRAY Protection XRAY VCC or VDD off or I C Reset
2
Figure 12 : Flyback Input Electrical Diagram
400
HFLY 12
Q1 20k
9109SN32.EPS 9109SN34.EPS 9109SN33.EPS
GND 0V
Figure 13
VCC
26 H-DRIVE
II.6 - Vertical Dynamic Focus The TDA9109/SN delivers a vertical parabola waveform on Pin 10. This vertical dynamic focus is tracked with VPOS and VAMP. Its amplitude can be adjusted. It is also affectedby Sand Ccorrections. This positive signal once amplified is to be sent to the CRT focusing grids.
I2C Drive on/off HORIZONTAL OUTPUT INHIBITION
I2C Ramp on/off VERTICAL OUTPUT INHIBITION
S R
Q
Horizontal Flyback 0.7V BOUT
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OPERATING DESCRIPTION (continued) III - VERTICAL PART III.1 - Function When the synchronization pulse is not present, an internal current source sets the free running frequency. For an external capacitor, COSC = 150nF, the typical free running frequency is 100Hz. The typical free running frequency can be calculated by : 1 f0 (Hz) = 1.5 10-5 COSC A negative or positive TTL level pulse applied on Pin 2 (VSYNC)as well as a TTLcomposite sync on Pin 1 can synchronize the ramp in the range [fmin , fmax]. This frequencyrange depends on the ext e rn al capa c it or con nect ed on Pin 2 2. A 150nF (5%) capacitor is recommended for 50Hz to 185Hz applications. The typical maximum and minimum frequency, at 25oC and without any correction (S correction or C correction), can be calculated by : f(Max.) = 3.5 x f0 and f(Min.) = 0.33 x f0 Figure 15 : AGC Loop Block Diagram
CHARGE CURRENT TRANSCONDUCTANCE AMPLIFIER REF 22 20 DISCH. SYNCHRO OSCILLATOR OSC CAP SAMPLING SAMPLING CAPACITANCE S CORRECTION VS_AMP SUB07/6bits COR_C SUB08/6bits C CORRECTION Vlow 18 BREATH
Sawth. Disch.
If S or C corrections are applied, these values are slighty affected. If a synchronization pulse is applied, the internal oscillator is synchonized immediately but its amplitude chan ges. An internal correction then adjusts it in less than half a second. The top value of the ramp (Pin 22) is sampled on the AGC capacitor (Pin 20) at each clock pulse and a transconduct ance amplifier modifies the charge current of the capacitor in such a way to make the amplitude again constant. The read status register provides the vertical LockUnlock and the vertical sync polarity information. We recommend the use of an AGC capacitor with low leakage current. A value lower than 100nA is mandatory. A good stability of the internal closed loop is reached by a 470nF 5% capacitor value on Pin 20 (VAGC).
VSYNCIN 2
POLARITY
23 VOUT VERT_AMP SUB05/7bits
9109SN35.EPS
VMOIRE SUB0C/5bits VPOSITION SUB06/7bits
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OPERATING DESCRIPTION (continued) III.2 - I2C Control Adjustments S and C correction shapes can then be added to this ramp. These frequency independent S and C corrections are generated internally. Their amplitudes are adjustable by their respective I2C registers. They can also be inhibited by their select bits. Finally, the amplitude of this S and C corrected ramp can be adjusted by the vertical ramp amplitude control register. The adjusted ramp is available on Pin 23 (VOUT) to drive an external power stage. The gain of this stage can be adjusted (25%) dependingon its register value. The mean value of this ramp is driven by its own I2C register (vertical position). Its value is VPOS = 7/16 VREF-V 300mV. Usually VOUT is sent through a resistive divider to the inverting input of the booster. Since VPOS derives from VREF-V, the bias voltage sent to the non-inverting input of the booster should also derive from VREF-V to optimize the accuracy (see Application Diagram). III.3 - Vertical Moire By using the vertical moire, VPOS can be modulated from frame to frame. This function is intended to cancel the fringes which appear when line to line interval is very close to the CRT vertical pitch. The amplitude of the modulation is controlled by register VMOIRE on sub-address 0C and can be switched-off via the control bit D7. III.4 - Basic Equations In first approximation,the amplitude of the ramp on Pin 23 (VOUT) is : VOUT - VPOS = (VOSC - VDCMID) (1 + 0.25 (V AMP)) with : - VDCMID = 7/16 VREF (middle value of the ramp on Pin 22, typically 3.5V) - VOSC = V22 (ramp with fixed amplitude) - VAMP = -1 for minimum vertical amplitude register value and +1 for maximum - VPOS is calculated by : VPOS = VDCMID + 0.3 VP with VP equals -1 for minimum vertical position register value and +1 for maximum The current available on Pin 22 is : 3 IOSC = VREF COSC f 8 with : COSC : capacitor connected on Pin 22 and f : synchronization frequency. III.5 - Geometric Corrections The principle is represented in Figure 16. Starting from the vertical ramp, a parabola-shaped currentis generatedfor E/W correction(also known as Pin Cushion correction), dynamic horizontal phase control correction, and vertical dynamic Focus correction. The parabola generator is made by an analog multiplier, the output current of which is equal to : I = k (VOUT - VDCMID)2 where VOUT is the vertical output ramp (typically between2 and5V)andVDCMID is3.5V(forVREF-V = 8V). One more multiplier provides a currentproportional to (VOUT - VDCMID)4 for corner correction. The VOUT sawtooth is typically centered on 3.5V. By changing the vertical position, the sawtooth shifts by 0.3V. In order to have good screen geometry for any end user adjustment, the TDA9109/SN has the "geometry tracking" feature, which allows generation of a dissymetric parabola depending on the vertical position. Due to the large output stage voltage range (E/W, Keystone, Corner), the combination of tracking function with maximum vertical amplitude, maximum or minimum vertical position and maximum gain on the DAC control may lead to the output stage saturation. This must be avoided by limiting the output voltage with apropriate I2C registers values. For the E/W part and the dynamic horizontal phase control part, a sawtooth-shapeddifferential current in the following form is generated: I' = k' (VOUT - VDCMID) Then I and I' are added and converted into voltage for the E/W part. Each of the three E/W components, and the two dynamichorizontal phasecontrolsmay be inhibited by their own I2C select bit. The E/W parabola is available on Pin 24 via an emitter follower output stage which has to be biased by an external resistor (10k to ground). Since stable in temperature, the device can be DC coupled with an external circuitry. The vertical dynamic focus is available on Pin 10. The dynamic horizontal phase control drives internally the H-position, moving the HFLY position on the horizontal sawtooth in the range of 1.4% TH both for side pin balance and parallelogram.
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OPERATING DESCRIPTION (continued) Figure 16 : Geometric Corrections Principle
V.Focus Amp 2 VDCMID (3.5V) 10 23 Vertical Ramp VOUT Parabola Generator 2 EW+ Amp Dynamic Focus
Corner VDCMID (3.5V) 24 EW Output Keystone
Sidepin Amp VDCMID (3.5V)
To Horizontal Phase Sidepin Balance Output Current
Parallelogram
III.6 - E/W EWOUT = 2.5V + K1 (VOUT - VDCMID)+ K2 (VOUT - VDCMID)2 + K3 (VOUT - VDCMID)4 K1 is adjustable by the keystone I2C register, K2 is adjustable by the E/W amplitude I2C register, K3 is adjustable by the corner I2C register. III.7 - Dynamic Horizontal Phase Control IOUT = K4 (VOUT - VDCMID)+ K5 (VOUT - VDCMID)2 K4 is adjustable by the parallelogram I2C register, K5 is adjustable by the side pin balance I2C register.
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OPERATING DESCRIPTION (continued) IV - DC/DC CONVERTER PART This unit controls the switch-mode DC/DC converter. It converts a DC constant voltage into the B+ voltage (roughly proportional to the horizontal frequency) necessary for the horizontal scanning. ThisDC/DC converter must be configured in stepup mode. It operates very similarly to the well known UC3842. IV.1 - Step-up Mode Operating Description - The power MOS is switched-on at the middle of the horizontal flyback. - The power MOS is switched-off when its current reachesa predeterminedvalue. For this purpose, a sense resistor is inserted in its source. The voltage on this resistor is sent to Pin16 (ISENSE). - The feedback (coming either from the EHV or from the flyback) is divided to a voltage close to Figure 17 : DC/DC Converter
I2 C DAC 7bits 8V 4.8V 20% 95dB A Inhibit SMPS BOUT 1/3 C2 1.2V 1.2V COMP 14 ISENSE 16 C3 Inhibit SMPS REGIN 15 1M 22k + L S Q R Soft Start
28
4.8V and compared to the internal4.8V reference (IVREF). The difference is amplified by an error amplifier, the output of which controls the power MOS switch-off current. Main Features - Switching synchronized on the horizontal frequency, - B+ voltage always higher than the DC source, - Current limited on a pulse-by-pulse basis. The DC/DC converter is disabled : - when VCC or VDD are too low, - when X-Ray protection is latched, - directly through I2C bus. When disabled, BOUT is driven to GND by a 0.5mA current source. This feature allows to implement externally a soft start circuit.
Iadjust
400ns
12V
TDA9109/SN
VB+
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INTERNAL SCHEMATICS Figure 18
5V 20k
Figure 19
5V
9109SN38.EPS
Figure 20
12V HREF 13
Figure 21
12V HREF 13
PLL2C
4
C0 5
9109SN40.EPS
Figure 22
HREF 13 12V HREF 13
Figure 23
PLL1F 7
R0 6
9109SN42.EPS
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9109SN41.EPS
9109SN39.EPS
Pins 1 -2 H/HVIN VSYNCIN
200
3
HLOCKOUT
TDA9109/SN
INTERNAL SCHEMATICS (continued) Figure 24
HREF 12V
Figure 25
5V 12V
HPOSITION 8
9109SN44.EPS
HMOIRE 9
9109SN45.EPS
Figure 26
12V
Figure 27
HREF 13
12V
12V
FOCUSOUT 10
HFLY 12
9109SN46.EPS 9109SN47.EPS
Figure 28
Figure 29
12V
REGIN 15
COMP 14
9109SN48.EPS
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INTERNAL SCHEMATICS (continued) Figure 30 Figure 31
12V
12V
ISENSE 16
BREATH 18
9109SN50.EPS
Figure 32
Figure 33
12V
VCAP 22
12V
VAGCCAP 20
Figure 34
9109SN52.EPS
Figure 35
12V
12V
EWOUT 24
VOUT 23
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9109SN53.EPS
9109SN51.EPS
TDA9109/SN
INTERNAL SCHEMATICS (continued) Figure 36
12V
12V
Figure 37
HOUT-BOUT Pins 26-28
XRAY 25
9109SN56.EPS 9109SN57.EPS
Figure 38
12V
Pins 30-31 SDA - SCL
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APPLICATION DIAGRAMS Figure 39 : Demonstration Board
J16 J15 1 J14 2 3 4 C39 22pF
+5V
+12V PC1 47k CC3 47pF +12V CC1 100nF TP13 J11
TP1
IC4 TDA9109/SN
1 H/HVIN
+5V L1 22H C30 100F R39 4.7k C32 100nF R29 4.7k R42 100 R41 100
CC2 10F
+5V 32
C40 22pF SCL SDA
13 14 15 16 17 18 19 20 21 22 23 24
TP16 TP17 J12
2 VSYNCIN
SDA 31 PWM4 PWM5 SCL SDA RST GND R G B TEST PWM6 PWM7
C45 10F
TP10
16 15 14 13 12 11 10 9
R49 22k
IC3 - STV9422
ICC1 MC14528
3 HLOCKOUT
SCL 30
+5V
VCC TA1
1
TB1 TA2
2
TB2 CDA
3
CDB IA
4
IB IA
5
IB QA
6
QB QA
7
QB GND
8
XTALOUT
XTALIN
CKOUT
HSYNC
VSYNC
PWM3
PWM2
PWM1
PWM0
PXCK
2
C7 22nF
4 PLL2C
FBLK
V DD
VCC 29 C6 100nF C5 100F
+12V
CC4 47pF +12V PC2 47k R35 10k HOUT C22 33pF R8 10k 2k R10 10k C25 33pF
C28 820pF 5%
5 C0
12
11
10
9
8
7
6
5
4
3
2
1
B+OUT 28 +12V R56 560 D2 1N4148
X1 8MHz C38 33pF C37 33pF
L2 22H
R43 10k +5V C42 1F R30 10k
TILT J13
R23 6.49k 1%
6 R0
GGND 27 R53 1k HOUT C49 100nF C48 10F
C43 47F
+12V
C13 10nF C31 4.7F R36 1.8k
7 PLL1F
HOUTCOL 26
8 HPOSITION XRAYIN 25
R7 10k TP14
C36 1F
+12V R37 27k R34 1k R15 1k R17 270k
E/W POWER STAGE
R31 27k R19 270k C11 220pF R38 2.2 3W
J8
C17 1F
9 HMOIRE
EWOUT 24
R45 33k
J1
HFLY J9 R25 1k
10 FOCUS
Q1 Q2 BC557 BC557
E/W
VOUT 23 +12V C12
DYN FOCUS
R24 10k
L4 47H
11 HGND
R9 470
R33 4.7k
R18 39k
Q3 TIP122
VCAP 22 150nF
R52 3.9k
C16 ( *) J19 1 2 3 4 CON4 JP1 C51 100nF REGIN R51 1k ISENSE C47 100pF GND R58 10 B+OUT +12V R75 10k R73 1M P1 10k R74 10k C60 100nF Q5 BC547 C50 10F HOUT L3 22H Q4 BC557 R57 82k
16 ISENSE 14 COMP 12 HFLY
VREF 21 C3 47F C15 D1 1n4001 C4 100nF R2 5.6k 7 R40 36k 2 6 3
C27 47F
C33 100nF
HREF
13 HREF
C14 470F
C9 100nF TP6
J2 +12V -12V TP4 TP3 J3
VAGCCAP 20 470nF VGND 19
C2 100nF
C10 100F 35V
TP7
J6 1
R50 1M
C46 1nF
15 REGIN
IC1 TDA8172
5 1 4 C10 -12V 470F C1 R3 220nF 1.5 C8 100nF R11 V YOKE 220 0.5W R4 1 0.5W
BREATH 18
R1 12k C41 470pF
2 3 J18
BGND 17
R5 5.6k
VERTICAL DEFLECTION STAGE
J17
TP8 EHT COMP
( * ) Optional
The difference with standard TDA9109 Application Diagram is the resistor divider 2k/2 o n Pin 9 (HMOIRE).
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R76 47k
R77 15k
TDA9109/SN
PACKAGE MECHANICAL DATA 32 PINS - PLASTIC SHRINK DIP
Dimensions A A1 A2 B B1 C D E E1 e eA eB L
Min. 3.556 0.508 3.048 0.356 0.762 0.203 27.43 9.906 7.620
Millimeters Typ. 3.759 3.556 0.457 1.016 0.254 27.94 10.41 8.890 1.778 10.16 3.048
Max. 5.080 4.572 0.584 1.397 0.356 28.45 11.05 9.398
Min. 0.140 0.020 0.120 0.014 0.030 0.008 1.080 0.390 0.300
Inches Typ. 0.148 0.140 0.018 0.040 0.010 1.100 0.410 0.350 0.070 0.400 0.120
Max. 0.200 0.180 0.023 0.055 0.014 1.120 0.435 0.370
2.540
12.70 3.810
0.100
0.500 0.150
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2 2
30/30
SDIP32.TBL
PMSDIP32.EPS

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